1. Field of the Invention
The present invention relates to ion implantation. More particularly, the present invention relates to a method of testing the level of ion implantation energy provided by ion implantation equipment.
2. Description of the Related Art
Part of the architecture of a prior art semiconductor device includes a twin well scheme as shown in FIG. 1. This typical twin well scheme has a core well having a p-type conductivity (Pwell CORE), and a peripheral well having a p-type conductivity (Pwell PERI) in a p-type substrate (P-sub). The twin well scheme is convenient to manufacture because both wells can be produced in a single process. However, independent biasing is impossible because the Pwells are formed directly in the p-type substrate (P-sub).
In order to overcome the shortcomings of this well scheme, most present devices employ a triple well scheme, as shown in FIG. 2. Independent biasing can be performed for each p-well under the triple well scheme. Also, the scheme provides a basis for enhancing the operating characteristics of transistors of a dynamic random access memory (DRAM) formed on the P-sub, for example.
More specifically, a DRAM cell region (memory cell region) is formed on the pocket p-well (Pwell CORE) surrounded by the deep n-well (Deep-Nwell). On the other hand, a peripheral (circuit) region of the DRAM is formed on a portion of the p-type substrate (P-sub) to the side of the deep n-well. The p-wells, as acceptors at the cell region and peripheral circuit region, can be discriminated from each other due to the provision of the n-well serving as a donor. Thus, these p-wells can undergo independent biasing.
Therefore, in this scheme, noise from the peripheral region is prevented from influencing the memory cell region, and the memory cell region can be controlled independently of the peripheral region. Accordingly, a short-channel effect of the peripheral region can be easily controlled. Also, the scheme facilitates the manufacturing of a relatively small substrate voltage generating circuit.
Now, when the DRAM is manufactured using this p-type substrate, n-channel MOS transistors are produced on the memory cell region, and n-channel and p-channel MOS transistors are produced on the peripheral region. In order to form an n-channel MOS transistor of the memory cell region, and n-channel and p-channel MOS transistors of the peripheral region in separate wells, the p-well of the memory cell region must be isolated from the p-type silicon substrate. It is therefore essential to employ the above-described triple well scheme in which the n-well is deeper than and encompasses the p-well (pocket well) in the memory cell region. Such technology is disclosed in U.S. Pat. No. 5,397,734 entitled “Method of Fabricating a Semiconductor Memory Device Having a Triple Well Structure”.
Designing an optimum triple well thus involves establishing a control for the depth of the n-well and the pocket p-well. To this end, the wells are formed by implanting ions into the substrate to the desired depth. Accordingly, controlling the very high level of the ion implantation energy used to form the deep n-well is a very important process in achieving the desired characteristic of the resultant semiconductor device. It is thus essential to check and clarify whether each piece of ion implantation equipment in a mass production line is emitting the desired (normal) level of ion implantation energy. It is also necessary to confirm whether all of the pieces of ion implantation equipment are outputting the same level of ion implantation energy.
Although ion implantation equipment is provided with a control apparatus capable of controlling the ion implantation energy, it is very difficult to check and clarify whether the actual level of the ion implantation energy is within normal parameters because the ion implantation energy is generally in a high voltage state on the order of hundreds or thousands of keV. In an attempt to confirm the level of ion implantation energy, the prior art ion implantation equipment for forming wells on a silicon substrate employs a process monitor comprising a secondary ion mass spectrometer (SIMS) or a sheet resistance (RS) measuring device to obtain a projected range of the energy of ions implanted into a silicon wafer.
The graph of FIG. 3 illustrates the results of an RS measurement in which the level of ion implantation energy was changed within a range of about 5% using conventional ion implantation equipment to produce three different wells in a silicon substrate. Referring to FIG. 3, it is evident that a definite projected value of ion implantation energy put out by the ion implantation equipment is difficult to obtain from a monitoring procedure using RS measurement.